GForce Programming
  Home     Greg's 68k Programming Reference Author Profile     Detached Solutions     Really Old News  

The 68k CPU


The TI-89 and TI-92 plus use a 10mhz (12mhz on HW2 calculators) Motorola 680000 processor.


The M68k processor contains eight Data Registers, eight Address Registers, a Program Counter (PC), and a Status Register (SR)

Data Registers

There are eight data registers; D0-D7. Each register can contain up to 32 bytes. The least significant bit is addressed as bit zero; the most significant bit is addressed as bit 31. When using data registers, only the appropriate portion is changed; the high bits are neither used nor changed.

Address Registers

There are eight address registers; A0-A7. Each register can contain up to 32 bits. The least significant bit is addressed as bit zero; the most significant bit is addressed as bit 31. Address registers do not support byte size operands. When using address registers, only word and long-word opperands are supported. When moving address or data to an address register, the whole register is affected. When working with words, they are sign extended to 32 bits. Register A7 is treated differently than the rest. It functions as the stack pointer. Often, it is refered to as SP. While any address register could function as SP, it is best to use A7 under normal conditions.

The Status Register (SR)

System Byte

User Byte

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Trace Bit   Supervisor Bit    

Interrupt mask

      X (Extend) N (Negative) Z (Zero) V (Overflow) C (Carry)


Operating Modes

The microprocessor executes instructions in one of two modes: user mode or supervisor mode. The user mode provides the execution environment for the majority of application programs. The supervisor mode, which allows some additional instructions and privileges, is used by the operating system and other system software.

Supervisor Mode

The supervisor mode has the higher level of privilege. The mode of the processor is determined by the S bit of the status register; if the S bit is set, the processor is in the supervisor mode. All instructions can be executed in the supervisor mode. The bus cycles generated by instructions executed in the supervisor mode are classified as supervisor references. While the processor is in the supervisor mode, those instructions that use either the system stack pointer implicitly or address register seven explicitly access the SSP.

User Mode

The user mode has the lower level of privilege. If the S bit of the status register is clear, the processor is executing instructions in the user mode. Most instructions execute identically in either mode. However, some instructions having important system effects are designated privileged. For example, user programs are not permitted to execute the STOP instruction or the RESET instruction. To ensure that a user program cannot enter the supervisor mode except in a controlled manner, the instructions that modify the entire status register are privileged. To aid in debugging systems software, the move to user stack pointer (MOVE to USP) and move from user stack pointer (MOVE from USP) instructions are privileged.

Copyright © 2000 - by Greg D. All Rights Reserved.

External Links
Detached Solutions
Techno-Plaza ASM Lessons
TIGCC Cross Compiler

GForce Programming